Partitioning a flash memory data storage device

ABSTRACT

A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of, and claims priority to, U.S.patent application Ser. No. 12/537,741, filed Aug. 7, 2009, entitled“Partitioning a Flash Memory Data Storage Device”, which, in turn,claims the benefit of U.S. Provisional Application No. 61/167,709, filedApr. 8, 2009, and titled “Data Storage Device” and U.S. ProvisionalApplication No. 61/187,835, filed Jun. 17, 2009, and titled“Partitioning and Striping in a Flash Memory Data Storage Device,” thedisclosures of which are incorporated by reference herein in theirentirety.

TECHNICAL FIELD

This description relates to a data storage device.

BACKGROUND

Data storage devices may be used to store data. A data storage devicemay be used with a computing device to provide for the data storageneeds of the computing device. In certain instances, it may be desirableto store large amounts of data on a data storage device. Also, it may bedesirable to execute commands quickly to read data from and to writedata to the data storage device.

SUMMARY

According to one general aspect, a method of partitioning a data storagedevice that includes a plurality of memory chips is disclosed. Themethod includes determining a number memory chips in the data storagedevice. A host coupled to the data storage device defines a firstpartition and a second of the data storage device, where the firstpartition includes a first subset of the plurality of memory chips andwhere the second partition includes a second subset of the plurality ofmemory chips. The first subset does not include any memory chips of thesecond subset and wherein the second subset does not include any memorychips of the first subset.

In another general aspect, a method of partitioning a data storagedevice that includes a plurality of memory chips is disclosed, in whicha physical configuration of the data storage device, including thenumber memory chips in the data storage device, and a partitioningscheme for the data storage device are read. A host coupled to the datastorage device defines a first partition and a second partition of thedata storage device, where the first partition includes a first subsetof the plurality of memory chips and the second partition includes asecond subset of the plurality of memory chips, and where the firstsubset does not include any memory chips of the second subset andwherein the second subset does not include any memory chips of the firstsubset. A logical to physical memory map is allocated for the firstpartition, and a logical to physical memory map is allocated for thefirst partition.

Implementations can include one or more of the following features. Datacan be written to the first partition while reading data from the secondpartition. Determining a number memory chips in the data storage devicecan include transmitting information from the data storage device to thehost indicating the number of memory chips in the data storage device.The host can define an address location in the data storage device towhich to write data from the host, where the address location specifiesthat the data be written to a specific one of the plurality of memorychips.

The data storage device can include a plurality of physical channels forcommunication of data between the host and the plurality of memorychips, each channel being operably connected to a different plurality ofthe memory chips, and then the number of physical channels can bedetermined. A first subset and a second subset of the channels can bedefined, where channels of the first subset of the channels are operablyconnected only to memory chips of the first subset of memory chips andwhere channels of the second subset of the channels are operablyconnected only to memory chips of the second subset of memory chips. Andthe host can define an address location in the data storage device towhich to write data from the host, where the address location specifiesthat the data be written to a specific one of the plurality of memorychips through a specific channel. The first partition can include memorychips that are operably connected to a single channel.

The host can re-define the first partition of the data storage device toinclude a third subset of the plurality of memory chips, where the thirdsubset is different from the first subset, and where the third subsetdoes not include any memory chips of the second subset and where thesecond subset does not include any memory chips of the third subset. Anindication that one of the memory chips in the first subset has failedor is approaching failure can be received, and then re-defining thefirst partition can include defining the third subset as the firstsubset of memory chips but for the memory chip that has failed or thatis approaching failure.

In another general aspect, an apparatus includes a data storage devicethat includes a plurality of memory chips, and a host operably coupledto the data storage device via an interface. The host includes aconfiguration detection engine configured to detect the number of memorychips in the data storage device, and a partition engine. The partitionengine is configured to define a first partition of the data storagedevice, where the first partition includes a first subset of theplurality of memory chips and to define a second partition of the datastorage device, where the second partition includes a second subset ofthe plurality of memory chips, and where the first subset does notinclude any memory chips of the second subset and where the secondsubset does not include any memory chips of the first subset.

In another general aspect, an apparatus includes a data storage devicethat includes a plurality of memory chips, and a host operably coupledto the data storage device via an interface. The host includes aconfiguration detection engine configured to read a physicalconfiguration of the data storage device, including the number memorychips in the data storage device and configured to read a partitioningscheme for the data storage device. The host also includes a partitionengine configured to define a first partition of the data storagedevice, where the first partition includes a first subset of theplurality of memory chips and to define a second partition of the datastorage device, where the second partition includes a second subset ofthe plurality of memory chips, and configured to allocate a logical tophysical memory map for the first partition and to allocate a logical tophysical memory map for the second partition. The first subset does notinclude any memory chips of the second subset, and the second subsetdoes not include any memory chips of the first subset.

Implementations can include one or more of the following features. Forexample, the data storage device can be configured to transmit, uponreceiving a command from the host, information from the data storagedevice to the host indicating the number of memory chips in the datastorage device. The host can also include an address assignment engineconfigured to assign a memory address to data to be written to the datastorage device, where the assigned memory address specifies that thedata be written to a specific one of the plurality of memory chips.

The data storage device can include a plurality of physical channels forcommunication of data between the host and the plurality of memorychips, with each channel being operably connected to a differentplurality of the memory chips. Then, the configuration detection enginecan be further configured to detect the number of channels in the datastorage device, and the partition engine can be further configured todefine a first subset of the channels, where channels of the firstsubset of the channels are operably connected only to memory chips ofthe first subset of memory chips, and where the partition engine can befurther configured to define a second subset of the channels, wherechannels of the second subset of the channels are operably connectedonly to memory chips of the second subset of memory chips.

The host can further include an address assignment engine configured toassign a memory address to data to be written to the data storagedevice, where the assigned memory address specifies that the data bewritten to a specific one of the plurality of memory chips through aspecific channel. The first partition can include memory chips that areoperably connected to a single channel. The partition engine can befurther configured to re-define the first partition of the data storagedevice to include a third subset of the plurality of memory chips, wherethe third subset is different from the first subset, and where the thirdsubset does not include any memory chips of the second subset andwherein the second subset does not include any memory chips of the thirdsubset. The partition engine can be further configured to receive anindication that one of the memory chips in the first subset has failedor is approaching failure; and re-defining the first partition toinclude the third subset of the plurality of memory chips can includedefining the third subset as the first subset of memory chips but forthe memory chip that has failed or that is approaching failure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an exemplary block diagram of a data storage device.

FIG. 2 is an exemplary block diagram of a FPGA controller that can beused in the data storage device of FIG. 1.

FIG. 3A is an exemplary block diagram of exemplary computing devices foruse with the data storage device of FIG. 1.

FIG. 3B is an exemplary block diagram of exemplary computing devices foruse with the data storage device of FIG. 1.

FIG. 4 is an exemplary flowchart illustrating an example process ofpartitioning the data storage device of FIG. 1.

FIG. 5 is another exemplary flowchart illustrating an example process ofpartitioning the data storage device of FIG. 1.

DETAILED DESCRIPTION

This document describes an apparatus, system(s) and techniques for datastorage. Such a data storage apparatus may include a controller boardhaving a controller that may be used with one or more different memoryboards, with each of the memory boards having multiple flash memorychips. The data storage apparatus may communicate with a host using aninterface on the controller board. In this manner, the controller on thecontroller board may be configured to receive commands from the hostusing the interface and to execute those commands using the flash memorychips on the memory boards.

FIG. 1 is a block diagram of a data storage device 100. The data storagedevice 100 may include a controller board 102 and one or more memoryboards 104 a and 104 b. The data storage device 100 may communicate witha host 106 over an interface 108. The interface 108 may be between thehost 106 and the controller board 102. The controller board 102 mayinclude a controller 110, a DRAM 111, multiple channels 112, a powermodule 114, and a memory module 116. The memory boards 104 a and 104 bmay include multiple flash memory chips 118 a and 118 b on each of thememory boards. The memory boards 104 a and 104 b also may include amemory device 120 a and 120 b.

In general, the data storage device 100 may be configured to store dataon the flash memory chips 118 a and 118 b. The host 106 may write datato and read data from the flash memory chips 118 a and 118 b, as well ascause other operations to be performed with respect to the flash memorychips 118 a and 118 b. The reading and writing of data between the host106 and the flash memory chips 118 a and 118 b, as well as the otheroperations, may be processed through and controlled by the controller110 on the controller board 102. The controller 110 may receive commandsfrom the host 106 and cause those commands to be executed using theflash memory chips 118 a and 118 b on the memory boards 104 a and 104 b.The communication between the host 106 and the controller 110 may bethrough the interface 108. The controller 110 may communicate with theflash memory chips 118 a and 118 b using the channels 112.

The controller board 102 may include DRAM 111. The DRAM 111 may beoperably coupled to the controller 110 and may be used to storeinformation. For example, the DRAM 111 may be used to store logicaladdress to physical address maps and bad block information. The DRAM 111also may be configured to function as a buffer between the host 106 andthe flash memory chips 118 a and 118 b.

In one exemplary implementation, the controller board 102 and each ofthe memory boards 104 a and 104 b are physically separate printedcircuit boards (PCBs). The memory board 104 a may be on one PCB that isoperably connected to the controller board 102 PCB. For example, thememory board 104 a may be physically and/or electrically connected tothe controller board 102. Similarly, the memory board 104 b may be aseparate PCB from the memory board 104 a and may be operably connectedto the controller board 102 PCB. For example, the memory board 104 b maybe physically and/or electrically connected to the controller board 102.

The memory boards 104 a and 104 b each may be separately disconnectedand removable from the controller board 102. For example, the memoryboard 104 a may be disconnected from the controller board 102 andreplaced with another memory board (not shown), where the other memoryboard is operably connected to controller board 102. In this example,either or both of the memory boards 104 a and 104 b may be swapped outwith other memory boards such that the other memory boards may operatewith the same controller board 102 and controller 110.

In one exemplary implementation, the controller board 102 and each ofthe memory boards 104 a and 104 b may be physically connected in a diskdrive form factor. The disk drive form factor may include differentsizes such as, for example, a 3.5″ disk drive form factor and a 2.5″disk drive form factor.

In one exemplary implementation, the controller board 102 and each ofthe memory boards 104 a and 104 b may be electrically connected using ahigh density ball grid array (BGA) connector. Other variants of BGAconnectors may be used including, for example, a fine ball grid array(FBGA) connector, an ultra fine ball grid array (UBGA) connector and amicro ball grid array (MBGA) connector. Other types of electricalconnection means also may be used.

The interface 108 may include a high speed interface between thecontroller 110 and the host 106. The high speed interface may enablefast transfers of data between the host 106 and the flash memory chips118 a and 118 b. In one exemplary implementation, the high speedinterface may include a Peripheral Component Interconnect Express(“PCIe”) interface. For instance, the PCIe interface may be a PCIe x4interface or a PCIe x8 interface. The PCIe interface 108 may include aPCIe connector cable assembly to the host 106. In this example, the 110may include an interface controller configured to interface between thehost 106 and the interface 108. The interface controller may include aPCIe endpoint controller. Other high speed interfaces, connectors, andconnector assemblies also may be used.

In one exemplary implementation, the communication between thecontroller board 102 and the flash memory chips 118 a and 118 b on thememory boards 104 a and 104 b may be arranged and configured intomultiple channels 112. Each of the channels 112 may communicate with oneor more flash memory chips 118 a and 118 b. The controller 110 may beconfigured such that commands received from the host 106 may be executedby the controller 110 using each of the channels 112 simultaneously orat least substantially simultaneously. In this manner, multiple commandsmay be executed simultaneously on different channels 112, which mayimprove throughput of the data storage device 100.

In the example of FIG. 1, twenty (20) channels 112 are illustrated. Thecompletely solid lines illustrate the ten (10) channels between thecontroller 110 and the flash memory chips 118 a on the memory board 104a. The mixed solid and dashed lines illustrate the ten (10) channelsbetween the controller 110 and the flash memory chips 118 b on thememory board 104 b. As illustrated in FIG. 1, each of the channels 112may support multiple flash memory chips. For instance, each of thechannels 112 may support up to 32 flash memory chips. In one exemplaryimplementation, each of the 20 channels may be configured to support andcommunicate with 6 flash memory chips. In this example, each of thememory boards 104 a and 104 b would include 60 flash memory chips each.Depending on the type and the number of the flash memory chips 118 a and118 b, the data storage 100 device may be configured to store up to andincluding multiple terabytes of data.

The controller 110 may include a microcontroller, a FPGA controller,other types of controllers, or combinations of these controllers. In oneexemplary implementation, the controller 110 is a microcontroller. Themicrocontroller may be implemented in hardware, software, or acombination of hardware and software. For example, the microcontrollermay be loaded with a computer program product from memory (e.g., memorymodule 116) including instructions that, when executed, may cause themicrocontroller to perform in a certain manner. The microcontroller maybe configured to receive commands from the host 106 using the interface108 and to execute the commands. For instance, the commands may includecommands to read, write, copy and erase blocks of data using the flashmemory chips 118 a and 118 b, as well as other commands.

In another exemplary implementation, the controller 110 is a FPGAcontroller. The FPGA controller may be implemented in hardware,software, or a combination of hardware and software. For example, theFPGA controller may be loaded with firmware from memory (e.g., memorymodule 116) including instructions that, when executed, may cause theFPGA controller to perform in a certain manner. The FPGA controller maybe configured to receive commands from the host 106 using the interface108 and to execute the commands. For instance, the commands may includecommands to read, write, copy and erase blocks of data using the flashmemory chips 118 a and 118 b, as well as other commands.

The memory module 116 may be configured to store data, which may beloaded to the controller 110. For instance, the memory module 116 may beconfigured to store one or more images for the FPGA controller, wherethe images include firmware for use by the FPGA controller. The memorymodule 116 may interface with the host 106 to communicate with the host106. The memory module 116 may interface directly with the host 106and/or may interface indirectly with the host 106 through the controller110. For example, the host 106 may communicate one or more images offirmware to the memory module 116 for storage. In one exemplaryimplementation, the memory module 116 includes an electrically erasableprogrammable read-only memory (EEPROM). The memory module 116 also mayinclude other types of memory modules.

The memory boards 104 a and 104 b may be configured to operate withdifferent types of flash memory chips 118 a and 118 b. In one exemplaryimplementation, the flash memory chips 118 a and the flash memory chips118 b may be the same type of flash memory chips including requiring thesame voltage from the power module 114 and being from the same flashmemory chip vendor. The terms vendor and manufacturer are usedinterchangeably throughout this document.

In another exemplary implementation, the flash memory chips 118 a on thememory board 104 a may be a different type of flash memory chip from theflash memory chips 118 b on the memory board 104 b. For example, thememory board 104 a may include SLC NAND flash memory chips and thememory board 104 b may include MLC NAND flash memory chips. In anotherexample, the memory board 104 a may include flash memory chips from oneflash memory chip manufacturer and the memory board 104 b may includeflash memory chips from a different flash memory chip manufacturer. Theflexibility to have all the same type of flash memory chips or to havedifferent types of flash memory chips enables the data storage device100 to be tailored to different applications being used by the host 106.

In another exemplary implementation, the memory boards 104 a and 104 bmay include different types of flash memory chips on the same memoryboard. For example, the memory board 104 a may include both SLC NANDchips and MLC NAND chips on the same PCB. Similarly, the memory board104 b may include both SLC NAND chips and MLC NAND chips. In thismanner, the data storage device 100 may be advantageously tailored tomeet the specifications of the host 106.

In another exemplary implementation, the memory board 104 a and 104 bmay include other types of memory devices, including non-flash memorychips. For instance, the memory boards 104 a and 104 b may includerandom access memory (RAM) such as, for instance, dynamic RAM (DRAM) andstatic RAM (SRAM) as well as other types of RAM and other types ofmemory devices. In one exemplary implementation, the both of the memoryboards 104 a and 104 may include RAM. In another exemplaryimplementation, one of the memory boards may include RAM and the othermemory board may include flash memory chips. Also, one of the memoryboards may include both RAM and flash memory chips.

The memory modules 120 a and 120 b on the memory boards 104 a and 104 bmay be used to store information related to the flash memory chips 118 aand 118 b, respectively. In one exemplary implementation, the memorymodules 120 a and 120 b may store device characteristics of the flashmemory chips. The device characteristics may include whether the chipsare SLC chips or MLC chips, whether the chips are NAND or NOR chips, anumber of chip selects, a number of blocks, a number of pages per block,a number of bytes per page and a speed of the chips.

In one exemplary implementation, the memory modules 120 a and 120 b mayinclude serial EEPROMs. The EEPROMs may store the devicecharacteristics. The device characteristics may be compiled once for anygiven type of flash memory chip and the appropriate EEPROM image may begenerated with the device characteristics. When the memory boards 104 aand 104 b are operably connected to the controller board 102, then thedevice characteristics may be read from the EEPROMs such that thecontroller 110 may automatically recognize the types of flash memorychips 118 a and 118 b that the controller 110 is controlling.Additionally, the device characteristics may be used to configure thecontroller 110 to the appropriate parameters for the specific type ortypes of flash memory chips 118 a and 118 b.

As discussed above, the controller 110 may include a FPGA controller.Referring to FIG. 2, an exemplary block diagram of a FPGA controller 210is illustrated. The FPGA controller may be configured to operate in themanner described above with respect to controller 110 of FIG. 1. TheFPGA controller 210 may include multiple channel controllers 250 toconnect the multiple channels 112 to the flash memory chips 218. Theflash memory chips 218 are illustrated as multiple flash memory chipsthat connect to each of the channel controllers 250. The flash memorychips 218 are representative of the flash memory chips 118 a and 118 bof FIG. 1, which are on the separate memory boards 104 a and 104 b ofFIG. 1. The separate memory boards are not shown in the example of FIG.2. The FPGA controller 210 may include a PCIe interface module 208, abi-directional direct memory access (DMA) controller 252, a dynamicrandom access memory (DRAM) controller 254, a command processor/queue256 and an information and configuration interface module 258.

Information may be communicated with a host (e.g., host 106 of FIG. 1)using an interface. In this example, FIG. 2, the FPGA controller 210includes a PCIe interface to communicate with the host and a PCIeinterface module 208. The PCIe interface module 208 may be arranged andconfigured to receive commands from the host and to send commands to thehost. The PCIe interface module 208 may provide data flow controlbetween the host and the data storage device. The PCIe interface module208 may enable high speed transfers of data between the host and thecontroller 210 and ultimately the flash memory chips 218. In oneexemplary implementation, the PCIe interface and the PCIe interfacemodule 208 may include a 64-bit bus. The bi-directional direct memoryaccess (DMA) controller 252 may be arranged and configured to controlthe operation of the bus between the PCIe interface module 208 and thecommand processor/queue 256.

The bi-directional DMA controller 252 may be configured to interfacewith the PCIe interface 208, and each of the channel controllers 250.The bi-directional DMA controller 252 enables bi-directional directmemory access between the host 106 and the flash memory chips 218.

The DRAM controller 254 may be arranged and configured to control thetranslation of logical to physical addresses. For example, in animplementation in which the host addresses the memory space usinglogical addresses, the DRAM controller 254 may assist the commandprocessor/queue 256 with the translation of the logical addresses usedby the host to the actual physical addresses in the flash memory chips218 related to data being written to or read from the flash memory chips218. A logical address received from the host may be translated to aphysical address for a location in one of the flash memory chips 218.Similarly, a physical address for a location in one of the flash memorychips 218 may be translated to a logical address and communicated to thehost.

The command processor/queue 256 may be arranged and configured toreceive the commands from the host through the PCIe interface module 208and to control the execution of the commands through the channelcontrollers 250. The command processor/queue 256 may maintain a queuefor a number of commands to be executed and order the commands using anordered list to ensure that the oldest commands may be processed first.The command processor 100 may maintain the order of the commandsdesignated for the same flash memory chip and may reorder the commandsdesignated for different flash memory chips. In this manner, multiplecommands may be executed simultaneously and each of the channels 112 maybe used simultaneously or at least substantially simultaneously.

The command processor/queue 256 may be configured to process commandsfor different channels 112 out of order and preserve per-channel commandordering. For instance, commands that are received from the host andthat are designated for different channels may be processed out of orderby the command processor/queue 256. In this manner, the channels may bekept busy. Commands that are received from the host for processing onthe same channel may be processed in the order that the commands werereceived from the host by the command processor/queue 256. In oneexemplary implementation, the command processor/queue 256 may beconfigured to maintain a list of commands received from the host in anoldest-first sorted list to ensure timely execution of the commands.

The channel controllers 250 may be arranged and configured to processcommands from the command processor/queue 256. Each of the channelcontrollers 250 may be configured to process commands for multiple flashmemory chips 218. In one exemplary implementation, each of the channelcontrollers 250 may be configured to process commands for up to andincluding 32 flash memory chips 218.

The channel controllers 250 may be configured to process the commandsfrom the command processor/queue 256 in order as designated by thecommand processor/queue 256. Examples of the commands that may beprocessed include, but are not limited to, reading a flash page,programming a flash page, copying a flash page, erasing a flash block,reading a flash block's metadata, mapping a flash memory chip's badblocks, and resetting a flash memory chip.

The information and configuration interface module 258 may be arrangedand configured to interface with a memory module (e.g., memory module116 of FIG. 1) to receive configuration information for the FPGAcontroller 210. For example, the information and configuration interfacemodule 258 may receive one or more images from the memory module toprovide firmware to the FPGA controller 210. Modifications to the imagesand to the firmware may be provided by the host to the controller 210through the information and configuration interface module 258.Modifications received through the information and configurationinterface module 258 may be applied to any of the components of thecontroller 210 including, for example, the PCIe interface module 208,the bi-directional direct memory access (DMA) controller 252, the DRAMcontroller 254, the command processor/queue 256 and the channelcontrollers 250. The information and configuration interface module 258may include one or more registers, which may be modified as necessary byinstructions from the host.

The FPGA controller 210 may be arranged and configured to cooperate andprocess commands in conjunction with the host. The FPGA controller 210may perform or at least assist in performing error correction, bad blockmanagement, logical to physical mapping, garbage collection, wearlevelling, partitioning and low level formatting related to the flashmemory chips 218.

FIG. 3A is a schematic block diagram of an apparatus 300 including adata storage device 302 having a plurality of flash memory chips 318 a,318 b, 318 c, 318 d, 318 e, 318 f, 318 g, 318 h, 318 i, 318 j, 318 k,318 l that are organized into a first partition 321 and a secondpartition 322. The first and second partition 321 and 322 definedifferent physical areas of storage space in the data storage device302, such that directories and files of different categories can bestored in the different partitions, or so that one partition can be usedfor different purposes than the other partition. The first partition caninclude a first subset of the flash memory chips 318 a-f, while thesecond partition can include a second subset of the flash memory chips318 g-1, where there are not any flash memory chips that are part ofboth partitions. That is, the boundary between the partitions 321 and322 is drawn between individual flash memory chips to ensure that anindividual flash memory chip does not belong to more than one partition.

Organizing the data storage device into two or more partitions can servea number of purposes. For example, operating system file stored on onepartition can be kept separate from user files stored on anotherpartition. Cache and log files that can change size dynamically andrapidly, potentially making a file system full, can be stored on onepartition and kept separate from other files stored on a differentpartition. Partitions can be used for multi-booting setups, which allowusers to have more than one operating system on a single computer. Forexample, a user could install Linux, Mac OS X, and Microsoft Windows oroperating systems on different partitions of the same data storagedevice and have a choice of booting into any operating system (supportedby the hardware) at power-up. Partitions can be used to protect orisolate files to make it easier to recover a corrupted file system oroperating system installation. For example if one partition is corruptedbut none of the other file systems are affected, the data on the storagedevice may still be salvageable. Using a separate partition forread-only data also reduces the chances of the file system on thatpartition becoming corrupted. Partitions also can raise overall computerperformance on systems where smaller file systems are more efficient.For example, large hard drives with only one NTFS file system typicallyhave a very large sequentially-accessed Master File Table (MFT), and itgenerally takes more time to read this MFT than the smaller MFTs ofsmaller partitions.

In another example embodiment, the data storage device 302 may be usedto store large amounts of data (e.g., many Gigabytes or Terabytes ofdata) that must be read quickly from the data storage device andsupplied to the host. For example, the data storage device can be usedto cache large volumes of publicly accessible information (e.g., a largecorpus of web pages from the World Wide Web, a large library ofelectronic versions of books, or digital information representing alarge volume of telecommunications, etc.) that can be fetched by thehost in response to a query. Thus, it can be important that the relevantdata be accessed and returned very quickly in response to a read commandissued by the host. However, the information stored in the data storagedevice also may need to be constantly updated to keep the information upto date as the relevant information changes. For example, if theinformation on the storage device relates to a corpus of web pages, theinformation stored on the storage device may need to be updated as theweb pages change and as new web pages are created.

In such a system, a partitioned flash memory data storage device 302 canoffer exceptional performance. In a flash memory storage device, writeoperations to a flash memory chip take much longer (e.g., 10-100 timeslonger) than read operations from a flash memory chip. Therefore,organizing the chips 318 a-1 of the data storage device into two or morepartitions, where the partitions are defined at boundaries betweendifferent chips, offers a way to ensure fast read operations while alsoallowing the information stored on the data storage device to be updatedin real time. For example, both partitions 321 and 322 can be used tostore a corpus of data (e.g., a corpus of web pages) to be served inresponse to queries and the individual partitions can alternate betweenserving the requests and being updated with new information. Forinstance, in a first time period the first partition 321 can be used toprovide the information to the host (e.g., information that may berequested in response to a user query), while the data on the secondpartition 322 is updated (e.g., in response to changes or additions tothe web pages of the corpus). Then, in a second time period, therecently updated second partition 322 can be used to provide theinformation to the host, while the data on the first partition 321 isupdated. This process can be repeated so that data is always served froma partition that acts as a read-only device, and therefore provides veryfast responses to read commands from the host without being slowed downby write commands, while the other partition is being updated with newinformation. Defining the partitions such that an individual flashmemory chip is included in only one partition ensures that no flash chipwill have data written to it and read from it at substantially the sametime, which would cause a delay is responding to a read request from thehost 350.

As discussed above, the memory chips 318 a-1 can be connected to acontroller that may include a FPGA controller 310. The FPGA controllermay be configured to operate in the manner described above with respectto controller 110 of FIG. 1 or of FPGA 210 of FIG. 2. The FPGAcontroller 310 may include multiple channel controllers 312 a, 312 b,312 c, 312 d, 312 e, 312 f to connect the multiple channels 112 to theflash memory chips 318 a-1. Of course, as described above, the storagedevice can include more than 12 flash memory chips, more than sixchannel controllers, and many more than two flash memory chips may beoperably connected to a channel controller across a physical channel.Thus, the implementation shown in FIGS. 3A and 3B is merely schematicfor clarity of illustration.

In one implementation, channel controllers 312 a, 312 b, 312 c, 312 d,312 e, 312 f can control channels that are operably connected to flashmemory chips that are part of each partition 321 and 322. For example,channel controller 312 a can be operably connected to memory chip 318 a,which is part of the first partition 321, and also to memory chip 318 g,which is part of the second partition 322. In such a configuration, atleast one memory chip in the first partition 321 is connected to eachcommunication channel between the data storage device 302 and the host,and at least one memory chip in the second partition 322 is connected toeach communication channel between the data storage device 302 and thehost 350. Such a configuration results in maximum parallelism ofcommunication between a partition 321 or 322 and the host, which canresult in fast read access and fast write times from and to the datastorage device 302.

In another implementation, approximately half the channel controllerscan be operably connected to flash memory chips in a first partition andapproximately half the channel controllers can be operably connected toflash memory chips in the second partition.

In another implementation, shown in FIG. 3B, flash memory chips 318 a,318 b, 318 c, 318 d, 318 e, 318 f, 318 g, 318 h, 318 i, 318 j, 318 k,318 l can be organized into a first partition 331, a second partition322, a third partition 333, and a fourth partition 334, where thedifferent partitions define different physical areas of storage space inthe data storage device 302, such that directories and files ofdifferent categories can be stored in the different partitions, or sothat one partition can be used for different purposes than the otherpartition. The first partition 331 can include a first subset of theflash memory chips 318 a-c. The second partition 332 can include asecond subset of the flash memory chips 318 d-f. The third partition 333can include a third subset of the flash memory chips 318 g-i. The fourthpartition 334 can include a fourth subset of the flash memory chips 318j-l. Among the different partitions 331, 332, 333, and 334 there are notany individual flash memory chips whose physical memory address space ispart of two or more partitions. That is, the boundaries between thepartitions 331, 332, 333, and 334 are drawn between individual flashmemory chips to ensure that an individual flash memory chip does notbelong to more than one partition.

In the system of FIG. 3B, a partitioned flash memory data storage device302 can offer exceptional performance, e.g., when used to store a corpusof data (e.g., a corpus of web pages) to be served in response toqueries, and the individual partitions can alternate between serving therequests and being updated with new information. For instance, in afirst time period the first, second, and third partitions 331, 332, and333 can be used to provide the information to the host (e.g.,information that may be requested in response to a user query), whilethe data on the fourth partition 334 is updated (e.g., in response tochanges or additions to the web pages of the corpus). Then, in a secondtime period, the recently updated fourth partition 334, along with thesecond and third partitions 332 and 332 can be used to provide theinformation to the host, while the data on the first partition 331 isupdated. Thus, data on each partition can be updated in round robinfashion, while query requests are served by the other partitions. Thisprocess can be repeated so that data is always served from partitionsthat act as read-only devices, and therefore provides very fastresponses to read commands from the host without being slowed down bywrite commands, while the other partition is being updated with newinformation. Defining four partitions results in redundancy ofinformation stored on the data storage device, so that if a partition,channel, or individual memory chip fails, such that one partition is nolonger usable, the remaining three partitions can continue to be used toprovide a data storage device in which each of the remaining partitionstakes turns being updated while the other remaining partitions servedata requests.

As described above, the data storage device 302 can be connected to ahost 350 though an interface 308, which can be a high speed interface,such as, for example a PCIe interface. The host can include, forexample, a processor 352, a first memory 354, a second memory 356, and apartition engine 360. The first memory 354 can include, for example, anon-volatile memory device (e.g., a hard disk) adapted for storingmachine-readable, executable code instructions that can be executed bythe processor 352. The code instructions stored on the first memory 354can be loaded into the second memory (e.g., a volatile memory, such as,a random access memory) 356 where they can be executed by the processor352 to create the memory device detection engine 358 and the partitionengine 360. The second memory can include logical blocks of “user space”devoted to user mode applications and logical blocks of “kernel space”364 devoted to running the lower-level resources that user-levelapplications must control to perform their functions. The memory devicedetection engine 358 and the partition engine 360 can reside in thekernel space 364 of the second memory 356.

The configuration detection engine 358 can be configured to detect thenumber of flash memory chips 318 on the data storage device 302, and thepartition engine 360 can be configured to define the first partition 321and the second partition 322 of the data storage device. Thus, theconfiguration detection engine 358 and the partition engine 360, whichrun on the host 350, can be used by the host to discover hardware deviceproperties of the data storage device 302 and then to define, via thehost, the partitions 321 and 322. In one implementation, theconfiguration detection engine 358 can issue a query command to the datastorage device, and in response to the query command the data storagedevice can return information to the host about, for example, the numberof flash memory chips 318, the size (e.g., as measured in bytes) of eachchip, the number of channels in the data storage device, the flashmemory chips to which each the channel controller 312 a-e is operablyconnected. Such information can be stored on the EEPROM 116 on the FPGA310 and/or on the EEPROM 120 a of the flash board of the data storagedevice 302. The configuration detection engine can poll the EEPROM 116or the EEPROM 120 a (e.g., during a boot-up operation of the host 350)to cause the data storage device to return such information to the host350. In another implementation, the host may poll the flash memory chips318 to provide the information about, for example, the number of flashmemory chips 318, the size (e.g., as measured in bytes) of each chip,the number of channels in the data storage device, the flash memorychips to which each the channel controller 312 a-e is operablyconnected.

The partition engine 360 can receive the information from the memorydevice detection engine 358 about the number of flash chips 318, thesize of each flash chip, the number of channels and the memory chips towhich each channels is operably connected, and, based on thisinformation, the partition engine can define a first partition 321 andsecond partition 322 in the data storage device 302 The partition enginerunning on the host 350 can define the first partition to include memoryblocks drawn from a first subset of the memory chips 318 and the secondpartition memory blocks drawn from a second subset of the memory chips318, where the first subset does not include any individual flash chipsof the second subset and the second subset does not include anyindividual flash chips of the first subset. The partition engine 360then can map the physical memory block addresses (which may include, forexample, a unique channel number, a unique flash memory chip number, anda block address within the flash memory chip) to logical addresses thatcan be used by application programs running the in the user space, suchthat the user space applications running on the host 350 can read datafrom the data storage device 302 and write data to the data storagedevice 302 with reference to the logical space addresses.

After a partition scheme of multiple partitions has been defined anddata has been stored on the flash memory chips of the data storagedevice 100, the device can store information about the partitioningscheme, e.g., on the memory 116, so that the when the device is bootedat a later time, it can communicate the partitioning scheme to the host106 for the host to use. For example, the device may maintaininformation about the physical configuration of the data storage device,including a number of flash memory chips in the device and about thepartitioning scheme, including which flash memory storage chips andchannels are associated with which partitions on the memory 116. Then,when the system including the host 106 and the data storage device 100is booted, the storage device 100 can communicate this information tothe host 106, e.g., in response to a read operation performed by theconfiguration detection engine 358 of the host 106. The partitioningengine 360 of the host 106 then can define the partitions for theoperating system and applications running on the host. For example, thepartitioning engine 360 can define a first and second partition based onthe information read from the storage device 100, where the first andsecond partitions do not include any of the same memory chips. Thepartitioning engine 360 also can allocate a logical to physical memorymap for the first and second partitions, so that they user-levelapplication programs can use logical addresses that then are mapped tophysical memory addresses of the flash memory chips of the storagedevice 100.

The partition engine 360 also can be used to re-define the firstpartition of the data storage device to include a third subset of theplurality of flash memory chips, where the third subset is differentfrom the first subset, and where the third subset does not include anyflash memory chips of the second subset and wherein the second subsetdoes not include any flash memory chips of the third subset. Forexample, with reference to FIG. 3A and FIG. 3B, a user may decide thatthe original partition scheme shown in FIG. 3A does not suit his or herneeds, and therefore may use the host to redefine the partitions 321 and322 (e.g., to include more or fewer flash memory chips in the particularpartitions) or to add additional partitions to the scheme. In oneimplementation, the first partition 321 can be redefined as partitions331 and 333. Allowing the user to define the partitions through the hostrather that forcing the user to accept a partition scheme that ispre-defined by, or pre-loaded in, the controller 310 gives the userflexibility to define partitions as he or she desires and to change thepartition scheme when the need arises. In another implementation, theimminent failure of one of the flash memory chips, e.g., 318 a, may bedetected by the host, and in response to this information, the partitionengine may re-define the first partition 321 to exclude the flash memorychip 318 a from the partition, i.e., as the originally defined firstpartition but for the memory chip 318 a. Thus, any number of partitionscan be defined (up to the number of flash memory chips 118 a and 118 bin the storage device 100), and different partitions within a partitionscheme can include different numbers of flash memory chips and caninclude different amounts of memory space.

The host also may include an address assignment engine 366 that canexist in the kernel 364 and that can assign physical memory addresses todata to be written to the data storage device 302. For example, anapplication running in user space 362 may call for data to be writtenfrom the host 350 to the data storage device 302, and the user spaceapplication may specify that the data be written to a particular logicalmemory address. The address assignment engine 366 may translate logicaladdresses into physical addresses that can include, for example, aparticular channel that the data should be written to, a particularflash memory chip operably connected to the specified channel to whichthe data should be written, and a particular physical block address ofthe specified memory chip to which the data should be written. In suchan implementation, the translation of logical addresses to physicalmemory space addresses can be performed by the address assignment engine366, such that the role of the DRAM controller 254 of the FPGA 210 isreduced or irrelevant.

FIG. 4 is an exemplary flowchart illustrating an example process 400 ofpartitioning the data storage device of FIG. 1, where the deviceincludes a plurality of flash memory chips. The process 400 can includedetermining a number of flash memory chips in the data storage device(402). For example, the configuration detection engine can query thedata storage device to gather information about the number of flashmemory chips in the data storage device. A first partition of the datastorage device can be defined, via a host coupled to the data storagedevice, where the first partition includes a first subset of theplurality of flash memory chips (404). A second partition of the datastorage device can be defined, via the host, where the second partitionincludes a second subset of the plurality of flash memory chips (406).As a result of this process it is ensured that the first subset does notinclude any flash memory chips of the second subset and that the secondsubset does not include any flash memory chips of the first subset.

Optionally, the process 400 can include writing data to the firstpartition while reading data from the second partition (408).Determining the number flash memory chips in the data storage device caninclude transmitting information from the data storage device to thehost indicating the number of flash memory chips in the data storagedevice (410). An address location in the data storage device to which towrite data from the host can be defined in the host, where the addresslocation specifies that the data be written to a specific one of theplurality of memory chips (412).

When the data storage device includes a plurality of physical channelsfor communication of data between the host and the plurality of flashmemory chips, with each channel being operably connected to a differentplurality of the memory chips, the process 400 can further includedetermining the number of physical channels (414), determining a firstsubset of the channels, where channels of the first subset of thechannels are operably connected only to memory chips of the first subsetof memory chips (416), determining a second subset of the channels,where channels of the second subset of the channels are operablyconnected only to memory chips of the second subset of memory chips(418), and defining, in the host, an address location in the datastorage device to which to write data from the host, wherein the addresslocation specifies that the data be written to a specific one of theplurality of memory chips through a specific channel (420). In addition,the process 400 can include re-defining, via the host coupled to thedata storage device, the first partition of the data storage device toinclude a third subset of the plurality of flash memory chips (422).

FIG. 5 is another exemplary flowchart illustrating an example process500 of partitioning a data storage device that includes a plurality offlash memory chips, The process 500 can include reading a physicalconfiguration and of the data storage device, including the number flashmemory chips in the data storage device (502). The process can alsoinclude reading a partitioning scheme for the data storage device (504).For example, the configuration detection engine can read the physicalconfiguration and the partitioning scheme from the memory 116 of thedata storage device. A host coupled to the data storage device candefine a first partition of the data storage device, where the firstpartition includes a first subset of the plurality of flash memory chips(506), and a logical to physical memory map for the first partition canbe allocated (508). The host can define a second partition of the datastorage device, where the second partition includes a second subset ofthe plurality of flash memory chips (510) and where the first subsetdoes not include any flash memory chips of the second subset and whereinthe second subset does not include any flash memory chips of the firstsubset, and a logical to physical memory map for the second partitioncan be allocated (512).

Implementations of the various techniques described herein may beimplemented in digital electronic circuitry, or in computer hardware,firmware, software, or in combinations of them. Implementations may beimplemented as a computer program product, i.e., a computer programtangibly embodied in an information carrier, e.g., in a machine-readablestorage device, for execution by, or to control the operation of, dataprocessing apparatus, e.g., a programmable processor, a computer, ormultiple computers. A computer program, such as the computer program(s)described above, can be written in any form of programming language,including compiled or interpreted languages, and can be deployed in anyform, including as a stand-alone program or as a module, component,subroutine, or other unit suitable for use in a computing environment. Acomputer program can be deployed to be executed on one computer or onmultiple computers at one site or distributed across multiple sites andinterconnected by a communication network.

Method steps may be performed by one or more programmable processorsexecuting a computer program to perform functions by operating on inputdata and generating output. Method steps also may be performed by, andan apparatus may be implemented as, special purpose logic circuitry,e.g., a FPGA or an ASIC (application-specific integrated circuit).

Processors suitable for the execution of a computer program include, byway of example, both general and special purpose microprocessors, andany one or more processors of any kind of digital computer. Generally, aprocessor will receive instructions and data from a read-only memory ora random access memory or both. Elements of a computer may include atleast one processor for executing instructions and one or more memorydevices for storing instructions and data. Generally, a computer alsomay include, or be operatively coupled to receive data from or transferdata to, or both, one or more mass storage devices for storing data,e.g., magnetic, magneto-optical disks, or optical disks. Informationcarriers suitable for embodying computer program instructions and datainclude all forms of non-volatile memory, including by way of examplesemiconductor memory devices, e.g., EPROM, EEPROM, and flash memorydevices; magnetic disks, e.g., internal hard disks or removable disks;magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor andthe memory may be supplemented by, or incorporated in special purposelogic circuitry.

To provide for interaction with a user, implementations may beimplemented on a computer having a display device, e.g., a cathode raytube (CRT) or liquid crystal display (LCD) monitor, for displayinginformation to the user and a keyboard and a pointing device, e.g., amouse or a trackball, by which the user can provide input to thecomputer. Other kinds of devices can be used to provide for interactionwith a user as well; for example, feedback provided to the user can beany form of sensory feedback, e.g., visual feedback, auditory feedback,or tactile feedback; and input from the user can be received in anyform, including acoustic, speech, or tactile input.

Implementations may be implemented in a computing system that includes aback-end component, e.g., as a data server, or that includes amiddleware component, e.g., an application server, or that includes afront-end component, e.g., a client computer having a graphical userinterface or a Web browser through which a user can interact with animplementation, or any combination of such back-end, middleware, orfront-end components. Components may be interconnected by any form ormedium of digital data communication, e.g., a communication network.Examples of communication networks include a local area network (LAN)and a wide area network (WAN), e.g., the Internet.

While certain features of the described implementations have beenillustrated as described herein, many modifications, substitutions,changes and equivalents will now occur to those skilled in the art. Itis, therefore, to be understood that the appended claims are intended tocover all such modifications and changes as fall within the scope of theembodiments.

1. (canceled)
 2. A method of partitioning a data storage device, themethod comprising: receiving, via an interface operably coupling a hostwith the data storage device, information indicating a number of aplurality of flash memory chips in the data storage device, a firstportion of the plurality of flash memory chips being implemented in afirst memory channel and a second portion of the plurality of flashmemory chips being implemented in a second memory channel; defining, bythe host, a first partition of the data storage device, the firstpartition including a first subset of the plurality of flash memorychips that includes one or more memory chips of the first memory channeland one or more memory chips of the second memory channel; and defining,by the host, a second partition of the data storage device, the secondpartition including a second subset of the plurality of flash memorychips that does not include any flash memory chips of the first subset,a boundary between the first partition and the second partition beingdefined by the first subset of memory chips and the second subset ofmemory chip.
 3. The method of claim 2, wherein the interface is a PCIeinterface.
 4. The method of claim 2, further comprising: transmittingfirst data, via the interface, from the host to the data storage device;and writing the first data to the first partition while reading seconddata from the second partition.
 5. The method of claim 2, furthercomprising defining, by the host, an address location in the datastorage device to which to write data from the host, wherein the addresslocation specifies that the data be written to a specific one of theplurality of memory chips.
 6. The method of claim 2, wherein the datastorage device includes a plurality of physical channels forcommunication of data between the host and the plurality of memorychips, each channel being operably connected to a different plurality ofthe memory chips, the method further comprising: determining a number ofthe plurality of physical channels; determining a first subset of thechannels, wherein channels of the first subset of the channels areoperably connected only to memory chips of the first subset of memorychips; determining a second subset of the channels, wherein channels ofthe second subset of the channels are operably connected only to memorychips of the second subset of memory chips; and defining, in the host,an address location in the data storage device to which to write datafrom the host, wherein the address location specifies that the data bewritten to a specific one of the plurality of memory chips through aspecific channel.
 7. The method of claim 6, wherein the second partitionincludes memory chips that are operably connected to a single channel.8. The method of claim 2, further comprising: re-defining, via the hostcoupled to the data storage device, the first partition of the datastorage device to include a third subset of the plurality of memorychips, wherein the third subset is different from the first subset, andwherein the third subset does not include any memory chips of the secondsubset.
 9. The method of claim 8, further comprising: receiving anindication that one of the memory chips in the first subset has failedor is approaching failure, wherein re-defining the first partitionincludes defining the third subset as the first subset of memory chipsbut for the memory chip that has failed or that is approaching failure.10. An apparatus comprising: a data storage device including a pluralityof memory chips, a first portion of the plurality of memory chips beingimplemented in a first memory channel and a second portion of theplurality of memory chips being implemented in a second memory channel;an interface operably coupled with the data storage device; and a hostoperably coupled with the data storage device via the interface, thehost including: a configuration detection engine configured tocommunicate with the data storage device, via the interface, to detect anumber of the plurality of memory chips in the data storage device; anda partition engine configured to define a first partition of the datastorage device, the first partition including a first subset of theplurality of memory chips and to define a second partition of the datastorage device, the second partition including a second subset of theplurality of memory chips, the first subset including one or more memorychips of the first memory channel and one or more memory chips of thesecond memory channel; the first subset not including any memory chipsof the second subset; and a boundary between the first partition andsecond partition being defined by the first subset of memory chips andthe second subset of memory chips.
 11. The apparatus of claim 10,wherein: the host is configured to transmit, via the interface, aninformation request command to the data storage device; and the datastorage device is configured to transmit, via the interface uponreceiving the information request command, information indicating thenumber of the plurality of memory chips in the data storage device. 12.The apparatus of claim 10, wherein the host further comprises an addressassignment engine configured to assign a memory address to data to bewritten to the data storage device, wherein the assigned memory addressspecifies that the data be written to a specific one of the plurality ofmemory chips.
 13. The apparatus of claim 10, wherein: the data storagedevice includes a plurality of channels for communication of databetween the host and the plurality of memory chips, each channel beingoperably connected to a different plurality of the memory chips, theconfiguration detection engine is further configured to detect a numberof the plurality of channels in the data storage device, the partitionengine is further configured to define a first subset of the channels,channels of the first subset of the channels being operably connectedonly to memory chips of the first subset of memory chips, and thepartition engine is further configured to define a second subset of thechannels, channels of the second subset of the channels being operablyconnected only to memory chips of the second subset of memory chips. 14.The apparatus of claim 13, wherein the host further comprises an addressassignment engine configured to assign a memory address to data to bewritten to the data storage device, the assigned memory addressspecifying that the data be written to a specific one of the pluralityof memory chips through a specific channel.
 15. The apparatus of claim13, wherein the second partition includes memory chips that are operablyconnected to a single channel.
 16. The apparatus of claim 10, wherein:the partition engine is further configured to re-define the firstpartition of the data storage device to include a third subset of theplurality of memory chips, the third subset is different from the firstsubset, and the third subset does not include any memory chips of thesecond subset.
 17. The apparatus of claim 16, wherein: the partitionengine is further configured to receive an indication, via theinterface, that one of the memory chips in the first subset has failedor is approaching failure, and re-defining the first partition toinclude the third subset of the plurality of memory chips includesdefining the third subset as the first subset of memory chips but forthe memory chip that has failed or that is approaching failure.
 18. Theapparatus of claim 10, wherein the interface is a PCIe interface.
 19. Amethod of partitioning a data storage device, wherein the deviceincludes a plurality of memory chips, the method comprising: reading, bya host via a PCIe interface operably coupling the host with the datastorage device, a physical configuration of the data storage device, thephysical configuration including a number of the plurality of memorychips in the data storage device, a first portion of the plurality ofmemory chips being implemented in a first memory channel and a secondportion of the plurality of memory chips being implemented in a secondmemory channel; reading, but the host via the PCIe interface, apartitioning scheme for the data storage device; defining, via by thehost, a first partition of the data storage device, the first partitionincluding a first subset of the plurality of memory chips; allocating,by the host, a logical to physical memory map for the first partition;defining, by the host, a second partition of the data storage device,the second partition including a second subset of the plurality ofmemory chips; and allocating, by the host, a logical to physical memorymap for the second partition, the first subset including one or morememory chips of the first memory channel and one or more memory chips ofthe second memory channel; the first subset not including any memorychips of the second subset; and a boundary between the first partitionand second partition is defined by the first subset of memory chips andthe second subset of memory chips.
 20. The method of claim 19, furthercomprising: transmitting, via the PCIe interface, first data from thehost to the data storage device; and by the data storage device, writingthe first data to the first partition while reading second data from thesecond partition.
 21. The method of claim 19, wherein the data storagedevice includes a plurality of physical channels for communication ofdata between the host and the plurality of memory chips, each channelbeing operably connected to a different plurality of the memory chips,wherein the physical configuration of the data storage device furtherincludes the number of the plurality of memory chips in the data storagedevice, the method further comprising: determining a first subset of thechannels, wherein channels of the first subset of the channels areoperably connected only to memory chips of the first subset of memorychips; determining a second subset of the channels, wherein channels ofthe second subset of the channels are operably connected only to memorychips of the second subset of memory chips; and defining, by the host,an address location in the data storage device to which to write datafrom the host, wherein the address location specifies that the data bewritten to a specific one of the plurality of memory chips through aspecific channel.